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Patents
Patents | ICS Patents | MMC Patents
SPT Patents |
| US Pat 7,244,674
| Process of forming a composite diffusion barrier in copper/organic low-k damascene technology
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| US Pat 7,203,387
| VLSI-photonic heterogeneous integration by wafer bonding
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| US Pat 7,164,837
| Method of fabricating optical waveguide devices with smooth and flat dielectric interfaces
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| US Pat 7,162,133
| Method To Trim And Smooth High Index Contrast Waveguide Structures
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| US Pat 7,002,175
| Method of Making Resonant Tunneling Diodes and CMOS Backend-Process-Compatible Three Dimensional (3-D) Integration
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| US Pat 6,990,327
| Wideband monolithic tunable high-Q notch filter for image rejection in RF application
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US Pat 6,913,994
| Method to form Cu/OSG dual damascene structure for high performance and reliable interconnects
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US Pat 6,908,825
| Method of making an integrated circuit inductor wherein a plurality of apertures are formed beneath an inductive loop
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US Pat 6,872,657
| Method to form copper seed layer for copper interconnect
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US Pat 6,849,293
| Method to minimize iso-dense contact or via gap filling variation of polymeric materials in the spin coat process
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US Pat 6,846,725
| Wafer-Level Package for Micro-Electro-Mechanical Systems
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US Pat 6,846,720
| Method to reduce junction leakage current in strained Silicon on Silicon-Germanium devices
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US Pat 6,743,713
| Method of forming dual damascene pattern using dual bottom anti-reflective coatings (barc)
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US Pat 6,730,591
| Method of using silicon rich carbide as a barrier material for fluorinated materials
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US Pat 6,716,570
| Low temperature resist trimming process
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US Pat 6,667,516
| RF LDMOS on Partial SOI Substrate
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US Pat 6,664,596
| Stacked LDD High Frequency LDMOSFET
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US Pat 6,617,241
| Method of Thick Film Planarization
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US Pat 6,551,937
| Process for device using partial SOI
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US Pat 6,534,374
| Single damascene method for RF IC Passive component integration in copper interconnect process
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US Pat 6,495,903
| Integrated circuit inductor
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US Pat 6,489,203
| Stacked LDD high frequency LDMOSFET
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US Pat 6,472,962
| Inductor-capacitor resonant RF switch
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US Pat 6,468,906
| Passivation of copper interconnect surfaces with a passivating metal layer
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US Pat 6,468,853
| Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner
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US Pat 6,461,902
| RF LDMOS on partial SOI substrate
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US Pat 6,436,810
| Bi-layer resist process for dual damascene
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US Pat 6,433,325
| Apparatus and method for image enhancement
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US Pat 6,429,129
| Method of using silicon rich carbide as a barrier material for fluorinated materials
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US Pat 6,424,044
| Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization
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US Pat 6,387,798
| Method of etching trenches for metallization of integrated circuit devices with a narrower width than the design mask profile
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US Pat 6,383,855
| High speed, low cost BiCMOS process using profile engineering
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US Pat 6,352,921
| Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization
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US Pat 6,242,344
| Tri-layer resist method for dual damascene process
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US Pat 6,235,591
| Method to form gate oxides of different thicknesses on a silicon substrate
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US Pat 6,222,187
| Multiwavelength imaging and spectroscopic photoemission microscope system
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US Pat 6,200,887
| Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits
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US Pat 6,133,079
| Method for reducing substrate capacitive coupling of a thin film inductor by reverse p/n junctions
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US Pat 6,121,616
| Combined infrared and visible light spectroscopic photoemission microscope
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US Pat 6,100,195
| Passivation of copper interconnect surfaces with a passivating metal layer
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US Pat 6,096,604
| Production of reversed flash memory device
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US Pat 5,991,044
| Method and apparatus for determining characteristics of microstructures utilizing micro-modulation reflectance spectrometry
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US Pat 5,851,925
| Staining technique for semiconductor device for SEM exposure
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US Pat 5,801,083
| Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners
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