Nano-Electronics

Strategy & Focus

• Si-Nanowire based device technology and circuit application
  
  This works demonstrates, for the first time, the integration of Gate-All-Around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach. With matching of the drive currents of n- and p-MOSFETs using different gate lengths to achieve symmetric pull-up and pull-down, sharp ON-OFF transitions with high voltage gains (e.g., ∆VOUT/∆VIN up to ~40 for VDD=1.2V) are obtained. The inverter maintains its good transfer characteristics and noise margins for wide range of VDD tested down to 0.4V. Individual transistors show excellent sub-threshold characteristics and drive currents. The results are discussed in light of the circuit performances reported for other advanced non-classical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realise CMOS circuit functionality is thus demonstrated. This work was presented in the European Solid-State Device Research Conference (ESSDERC) 2007 in Germany.
  

• Device physics
  
  Gate-all-around n-MOSFETs with Si-nanowire (~7nm) as the channel body are fabricated and characterised for their low-temperature behaviour (~5 to 295K). IDS-VGS characteristics at low VDS (~50mV) exhibit a decrease in current with decreasing temperature in strong inversion up to about ~200K. However, at high VDS, drain current reverts to typical temperature behaviour, i.e., IDS increases with the reducing temperature due to increase in phonon-limited mobility (μph). It is inferred that at low VDS, the enhancement in μph at reduced temperature could be possibly masked by the inter-sub-band scattering on account of sub-band splitting due to quantum-confinement effects as indicated by sub-band calculations for nanowire structures. This work was published in IEEE Electron Device Letters in October 2007.

• Novel devices
  
  P-channel omega-gated SiGe nanowire FETs with high-k/metal gate fabricated using a top-down approach was demonstrated for the first time. By using a two-dimensional Ge condensation technique, almost ~70% Ge in the SiGe nanowire channel was achieved. The diameters of SiGe nanowires formed using this top-down approach are around 13nm. Excellent performance has been achieved with low DIBL, acceptable Ion-Ioff ratio (105) and sub-threshold swing. SiGe nanowire transistors greatly outperform their planar counterparts. Even better performance can be expected when the gate lengths are scaled down. With process optimisation, this top-down approach can potentially allow for the integration of nearly pure Ge nanowire transistors into CMOS logic circuits. This work was presented in the International Conference on Solid State Devices and Materials (SSDM) 2007.

Significant Results

CMOS Compatible Si-Nanowires based Logic Gates

The technology has reached a critical milestone, with the previously established Si/Ge-nanowires module, by realising and demonstrating the functional logic circuits for the first time:

• The CMOS inverters exhibit excellent transfer characteristics down to very low voltage (e.g., 0.2V), featuring appreciable noise margin (NML=0.31V, NMH=0.48V at VDD=1V), good gain (>55 at VDD=1V and ~18 at VDD=0.2V), and low switching currents (~160 nA at VDD=1V and 2.5pA at VDD=0.2V). These performances strongly suggest the good potential for low voltage/low power applications.
• The technology exhibits excellent high-yield, e.g., fully functional ring Oscillators up to 41-stages are demonstrated

This technology signifies a step closer to the integration of nanostructure-based electronic building blocks with other wire-based applications such as bioelectronics.

Tilted view SEM image of fabricated Si-nanowire 3-stage ring-oscillator with 2-stage buffer for signal probing.	41-stage ring oscillator waveforms for Vdd=1.2V. Frequency of the oscillation is ~1.5MHz, and Lg=0.5um.

Home | Top