Electronic products today demand low-cost, miniaturisation, a quicker time to market and the integration of different functional chips in a single module - such as digital, RF, analog, MEMS and optical chips, with each new generation requiring an even higher density of integration and functionality. Advanced packaging and interconnect technologies, such as fine pitch flip chip, embedded wafer level packaging and Through-Silicon Via (TSV) enable the jump from 2D chip layouts to 3D chip stacks, offering greater density in the same footprint, as well as improved functionality, higher performance and lower cost.

The Interconnect and Packaging Programme (IPP) at IME has been the focus on strategic research areas in the research and development of 3DIC and TSI platform with TSV technologies, 3D stacking with C2W and W2W bonding technologies, embedded wafer level packaging, Integrated Passive Device (IPD) with Si or polymer substrate, MEMS packaging, electrical, thermal, mechanical design, materials, process and reliability.