Project:
Silicon-Stacked Module and Pb-free High Power Flip Chip Packaging
After a 20-month period investigating chip and substrate design with structural optimisation, and evaluating underfill and thermal interface materials and assembly process optimisation, the EPRC VII Consortium team delivered a reliable Flip Chip Ball Grid Array ( FCBGA) package with high density multi-layered build-up substrate for 17.5mm x 17.5mm chip size and 150dm bump pitch with SnAg solder. The FCBGA package is capable of achieving stringent JEDEC reliability test requirements for moisture sensitivity under Pb free reflow condition and temperature cycling test. For the Silicon-Stacked Module, a new approach of stacking modules was adopted, using silicon as carrier. Silicon carrier stacking is a step towards wafer level stacking, which offers the potential for reduced manufacturing cost, high performance interconnects and high packing density.
The team developed processes for fine pitch flip-chip bumping, thin flip-chip attachment, and solder ball attachment to the carrier. Known good dies (KGD) were flip-chip attached to the silicon carrier to form known good carriers (KGC). KGC were stacked on the PCB sequentially one over the other to form 3-level Stacked Silicon Module. Assembly technologies were developed and the target module height of 2.4 to 2.5mm was achieved.
Failure analysis of a stacked module threw up a new challenge which was overcome using a technique developed earlier by IME – active thermography – to locate interconnection with resistive or open failure. The technique was successfully demonstrated to be capable of detecting failure locations below six stacked-up layers.
The developed Silicon-Stacked Module, with three stacks, flip chip and glass cap assembled on the PCB, was finally tested for reliability, and found to meet signal transmission up to ~ 2.5GHz bandwidth, which is suitable for 5 Gbps signal; 5 watts heat dissipation in natural convection environment and 20 watts with air cooled solution; and demonstrated improved solder joint fatigue life by five times with board level underfill.
The technologies developed take functional integration to a higher level, enabling more sophisticated features in electronic gadgets.
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| Cross section of the silicon stacked module |
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Silicon module without glass cap |
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Silicon stacked module mounted on the board |
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Wire Bond on the silicon carrier with thin film metallization |
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