As demand for more and affordable functions in electronics increases, System-in-Package (SiP) is the emerging solution for complex system integration, allowing different ICs, passive components, etc, to be amalgamated onto a substrate to form a functional block.

The three projects under EPRC 8 are:

1. Fine-pitch large die FCBGA - to come up with a universal test vehicle substrate design that accommodates different die sizes of up to 25mm x 25mm for assembly and reliability assessment, as well as large die Cu/low-k interconnects;
2. Stacked silicon module with embedded passives – to develop 3D Silicon-Stacked Modules with embedded passives, including design and characterisation of the electrical performance for digital/RF mixed signal applications and mechanical reliability;
3. Cu low-k device packaging - to produce and assess the reliability of Cu/low-k stack die package as well as leadfree Cu/low-k Wafer Level Package.

Other than MSPI, which consists of A*STAR research institutes IME, IMRE, IHPC and SIMTech, a total of 16 companies are participating in this EPRC 8 Consortium. They include Agere, AMD, ASM, Infineon, STATSChipPAC and UTAC. Many of these have supported the EPRC since its inception, either as core or associate members.