The EPRC completed its seventh programme in 2005 to develop new packaging methodologies for optimised electrical, thermal, optical and reliability performance. The two projects under the programme were Silicon-Stacked Module and Pb-free High Power Flip Chip Packaging.

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The EPRC is currently in its eighth consortium programme. As demand for more and affordable functions in electronics increases, System-in-Package (SiP) is the emerging solution for complex system integration, allowing different ICs, passive components, etc, to be amalgamated onto a substrate to form a functional block.

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The EPRC intends to take technology developments even further in its next consortium programme – EPRC 9, which will be launched in October 2007.

The research areas under EPRC 9 include:

• Development of hybrid 3D stack and demonstration of optical interconnects - to demonstrate high frequency interconnect on FR4 optical PCB with low cost stacked dies;
• TSV technology for large die Cu/low K chip packaging- to develop TSV technology for large die Cu/low K chip with very fine pitch interconnection;
• Embedded micro wafer level packaging - to develop embedded wafer level packaging solution simultaneously achieving wafer level reconstruction of multiple chip using fan out interconnects, embedding passives design and fabrication, and assessment of electrical and reliability performance;
• Low temperature bonding for high density 3D interconnection - to develop a low temperature bonding for high density interconnection by Chip to Chip (C2C), Chip to Wafer (C2W) and Wafer to Wafer (W2W) bonding method to meet the higher reflow temperature.

The Drop Impact Reliability Consortium aims to advance the understanding of reliability of electronic interconnects to drop impact with the goals of providing practical solutions to the microelectronics packaging industries. It was initiated by IME and three industry partners – Freescale Semiconductor, Philips and ASE in June 2006.

This is the first IME consortium addressing the challenge of characterising solder joints at component and board level. The 18-month-long consortia project also attempts to address the challenge of a model for predicting the fatigue life of solder joints in drop impact.

In the study, the solder joints are subjected to high strain rate that is equivalent to that experienced in a portable product in the event of accidental drop-impact. This will generally raise the yield strength of the ductile solder while lowering the fracture strength of the brittle intermetallics.

Discovering defective board assembly at the final inspection when subjected to JEDEC standard drop test is extremely costly. A component level QC test is an ideal solution as it can be used for quality control of the ball attachment process on the substrate as well as in quality inspection of raw materials such as substrates and solder balls. The fatigue properties of the solder joints at high strain rate which are essential for establishing a qualification test and a failure model are lacking.

The project aims to address the issues by providing solutions in test methodologies and failure model.

High speed cyclic bend tester for reproducing the shock spectrum in a product drop

IME has forged a collaboration with the Packaging Research Centre at the Georgia Institute of Technology (PRC-GT) to promote research and training in electronics packaging, and to stimulate the application of useful knowledge to technological innovation by means of a membership supported research for Embedded Actives & Passives (EMAP).

Initiated in January 2007, EMAP is a global industry-academia consortium for new and advanced embedded actives and passives for System-on-a Package (SOP) technology and is specifically focused on supporting the emerging digital convergence of mobile and desktop applications. IME is a research partner of PRC-GT and is working on three projects as part of the EMAP programme. These are:

• Ultra thin silicon die – to develop wafer thinning method to achieve ultra thin wafer of 30 micron;
• Ultra thin device handling and characterisation – to study the ultra thin die handling and silicon die reliability in an embedded module;
• Chip-last approach device attachment using self-assembly processes – to develop a process for ultra thin die to organic laminates.

To join the EMAP consortium, contact Venkatesh Sundaram of PRC-GT at vsunda@ece.gatech.edu.

The mission of the Singapore SME Packaging Consortium (SSPC) is to train skilled personnel in electronics packaging, improve capabilities of SMEs and enhance the vibrancy and competitiveness of the SME industry through activities of the consortium.

One key feature of SSPC is the virtual R&D lab, where members have access to IME’s packaging lab and are able to leverage on IME’s design and modeling capabilities for prototyping and small sample size packaging. In addition, members also benefit from the regular industry updates, training courses and hands-on exposure provided by the SSPC. Members can also leverage on IME’s IP for product development and joint projects.

Annual membership fees for SSPC are S$2,500 for companies with fixed asset less than S$15 million, and S$5,000 for companies with fixed asset exceeding S$15 million and revenue less than S$200 million. For enquiries on SSPC, contact Dr Yoon Seung Uk at yoonsw@ime.a-star.edu.sg.