Tunneling field effect transistor (TFET) represents an attractive and practical paradigm that can potentially provide relief to the increasing power dissipation with device scaling. It is essentially a gate tunable p+/i/n+ diode functioning through tunneling of carriers from source to channel, as the name imply. TFET possess low off-state leakage current (I_OFF), weak temperature dependence, and more importantly a subthreshold slope (SS) smaller than the thermally limited 60 mV/decade, making it ideal for emerging ultra-low power green electronic applications.

The schematic diagram and the band diagram of a TFET device is as shown in Fig. 1. Interestingly, the same device can work either n- or p-type device. When V_G>0V, the tunneling barrier is at p+/i junction, electron being the charge carrier, device behaves as n-TFET, while for V_G<0V, the tunneling barrier is at i/n+ junction, and device behaves as p-TFET with hole being the carrier.

Fig.1: TFET schematic (left) and corresponding operation through band-diagram (right).

Despite the extraordinary promising features, TFET remained in research for many years mainly due to issues such as low on-current, ambipolar behavior, and lithography unfriendly source/drain implant patterning. All these problems, however, could be solved in vertical gate-all-around (GAA) nanowire device architecture by independently controlling source and drain implants and thermal budgets, demonstrated by IME researchers in collaboration with NTU. They used vertical Si-nanowire technology platform reported earlier and fabricated GAA TFET devices on vertical Si-wires of diameter ~ 70 nm with gate length of 200 nm and gate oxide thickness of 4.5 nm.

Shown in Fig. 2 are the transfer characteristics the device. Although the SS (~70mV/decade) remained higher than KT/q (likely due to non-abrupt tunneling junction), without using any performance boosters, the GAA Si-nanowire device performed exceptionally well with record high on-current (~50µA/µm; about 10x to the best reported), low off-state current, and low DIBL. The performance improvements are attributed to excellent gate electrostatic control in GAA nanowire architecture leading to enhanced tunneling along with ultimate scalability. In addition, the credit for suppressing the parasitic ambipolar effect is given to the inherent asymmetry in the S/D junctions - top junction being more abrupt than bottom junction as a result of different thermal budgets.

Fig. 2: Transfer characteristics of n-TFET.

The TFET is a promising candidate for the succession of the MOSFET and the vertical nanowire GAA architecture demonstrated here makes it even more attractive due to the improved scalability, density and performance without additional complexity. Thus the vertical nanowire GAA TFET is an excellent candidate for future handheld-mobile and implantable devices/systems requiring ultra low power consumption required by an extremely large market.