IME researchers have successfully developed a method for channel mobility extraction with the capability of measuring capacitance down to a fraction of a Femto Farad.

Carrier transport characterization in nano-scale devices is challenging in view of the reducing number of carriers (charge) in the channel or reducing gate capacitance. In MOSFET based devices, the carrier charge is obtained from the capacitance voltage characteristics by integrating the capacitance and factoring this charge into the current voltage characteristics to obtain the carrier velocity (or mobility) as a function of terminal biases or fields. As the capacitance continues to decrease in magnitude, its measurement using conventional ac bridge technique becomes tricky. In fact, the capacitance of a single channel (or minimum geometry) of any nano-scale device is already far smaller than the lower limit of any standard ac bridge based instrument.

An alternative scheme to measure the low value of capacitance in case of interconnects, christened as Charge-Based Capacitance Measurement (CBCM), was proposed by Berkeley group [1]. IME has implemented this scheme for characterization of gate capacitance (Cgs) of nanowire CMOS transistors. The principle of measurement is explained in Fig.1.

When the upper switch is closed with the help of signal INP1, the DUT gate is charged to VDD. The gate is discharged to Gnd (VSS) by closing of the lower switch with the help of signal INP2. The charging and discharging paths are isolated and measurement of the average (DC) charging (or discharging) current which is simply a measurement of the rate at which charge flows to (from) the DUT gate is facilitated. This current divided by frequency of charging (discharging) gives the charge, which, in turn, yields the capacitance when divided by VDD (linear capacitors) or differentiated with respect to VDD (non-linear capacitors such as FET gates).

This simple method suffers from two major sources of errors: (i) charge injection which leads to extra charge flow to the VDD (VSS) during switching and (ii) charging (discharging) of parasitic capacitances associated with the DUT gate node. Both these difficulties are resolved using a two step measurement [2] – in the first step the total capacitance (DUT + Charge Injection + Parasitic) are measured, and, in the second step, the other terminal of the DUT is charged to VDD before charging the gate to VDD by applying a pulse at that terminal. The difference between the two capacitances yields the DUT gate capacitance free from charge injection as well as the parasitic.

IME has successfully implemented this scheme for nanowire transistors for channel mobility extraction and have measured the capacitance down to 400aF (400x 10-18 Farads). In conjunction with Id-Vg characteristics at low drain voltage, the channel carrier mobility as a function of gate voltage (Vgs) has been extracted from a single channel of NW transistors (Fig.2). It is worth while to mention that all devices (DUT as well as the switches) used in the circuit are nanowire devices in our case.

Fig.1: The schematics of the CBCM measurements.

Fig.2 Id-Vd characteristics of a PMOS device and C-V characteristics measured using CBCM. Also shown is the mobility variation of holes in the NW channel with the gate voltage.

[1] Chen etal., IEDM, 1996, p.69.
[2] Chang et al., IEEE, EDL, May, 2006, p.390.