The gate-all-around (GAA) silicon nanowire (SiNW) transistors are considered as one of the most promising candidates for ultra-scaled low power logic and non-volatile memory device applications owing to their superior short channel controllability. While electrostatic gate control improves with scaling of the channel body thickness, high series resistance, due to narrow wired source and drain (S/D) extension regions and further by reduction in dopant ionization with wire diameter, limits the drive performance. The low resistivity silicided metallic extensions are therefore needed. However, with reduced wire diameter, the silicide formation in nanowire leads to fast lateral encroachment which demands a precise control over the position of silicon-to-silicide junction when gate lengths are short.

IME researchers have successfully developed a silicon nanowire Nickel silicidation process and integrated that with their GAA nanowire device platform to fabricate a high performance ultra scaled GAA SiNW FETs suitable for 22 nm technology node and below. At a fixed IOFF of 10nA/µm, compared with reference (non-metallic S/D extensions), the salicided nanowire devices with Lg=8 nm and NW diameter ~ 10 nm show 580% enhancement in ION from 350 µA/µm to 2200 µA/µm. This improvement is attributed to the reduction in extension series resistance caused by low resistivity NiSi metallic nanowires S/D extensions. 4 nm thick Ni layer was found optimum for 10 nm thick nanowire.

Figure: (Left) TEM micrograph of the channel cross section showing GAA structure. The tilted top view image of the Lg=8 nm device taken after Ni salicidation is shown as inset. (Right) IDS-VG characteristics for SiNW devices w/ and w/o salicidation. Diameter of the nanowire is 10nm, SS is 73mV/dec and DIBL is 28mV/V. Significant drive current enhancement is clearly seen.