Gate-all–around (GAA) nanowire FET has attracted much attention for better electrostatic control as compared to other gate designs such as double or tri-gated transistors. It is challenging to obtain small channel lengths out of relatively long nanowires and thus resulting in devices with high extension resistance. Vertical GAA transistor has the potential to combine good performance with high device density. The application of vertical transistors in memory devices is especially sought after, due to its potential in shrinking individual devices and capability of multilevel memory structures 3-dimensionally.

Most proposed vertical transistor structures utilize thick pillars. The patterning of small dots for making nanowires is challenging due to high background transmission in the mask. Lifting of the tiny dots during rinse process can also be a serious problem. Therefore, the direct patterning and etch process cannot result in vertical nanowire structure with good yield. Non-lithographic methods such as vapour-liquid-solid mechanism and molecular beam epitaxy can produce very thin nanowires. However, nanowires thus produced are randomly distributed and complicated processes are required to assemble them into functional devices.

IME researchers have presented a vertical Gate-All-Around (GAA) silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS-compatible technology. High aspect ratio (up to 50:1) vertical nanowires with diameter ~ 20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. N-MOS devices thus fabricated with gate length ~150 nm showed excellent transistor characteristics with large drive current (1.0× 103 μA/μm), high Ion/Ioff ratio (~107), good subthreshold slope (~80mV/ dec) and low DIBL (~10mV/V). Along with good electrical characteristics, the use of low cost bulk wafers and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.

SEM pictures of device fabrication: (a) Vertical nanowire with diameter ~20nm; (b) After gate patterning by lithography but before exposing the drain (the tip of the pillar) of the transistor; (c) After the drain (pillar tip) is exposed. Metal contacts are made with such device structure; (d) Vertical nanowire arrays with pitch of 500nm. Nanowires are 1 µm tall with a diameter of ~20nm.	Transistor Performance: (a) Id-Vg curve, the threshold voltages at Vd= 1.2V and Vd= 0.05V are -0.25V and -0.23V respectively; (b) Id-Vd curve of the same device; each pair of curves contains Id-Vd of the same gate voltage. The upper curve is obtained when the nanowire tip serves as the source, while the lower curve is obtained when the nanowire tip serves as the drain.