IME researchers have developed a fine pitch wafer level packaging for Cu/Low-k device structures and investigated the assembly and reliability of these fine pitch WLP packages with two different solder interconnects (copper pillar with SnAg solder tip and SnAg solder interconnects). The team also conducted the detailed parametric study to optimise the chip level and package level reliability of the fine pitch Cu/Low-k WLP.
In this project, the researchers developed a dicing process for the bumped Cu/Low-k device wafer using PEDL (polymer encapsulated dicing line) method to avoid the peeling in Cu/Low-k layers. Test chip of 7x7 mm with 128 I/Os at 300 um pitch fabricated and assembled on 2-layer high Tg FR4 substrate with and without no-flow underfill. Cu/Low-k WLPs are subjected to high temperature storage (HTS) test, drop test and thermal cycling (TC) test to evaluate their reliability. Packages with both SnAg and copper pillar interconnects and without no-flow underfill passed 1000 hours HTS test, and passed the JEDEC drop test with no-flow underfill. Packages with solder interconnect and no-flow underfill showed better performance in the TC test.
For the copper interconnects, the team found re-distribution line (RDL) failure at the base of the copper pillar due to the stress induced on the RDL by rigid copper pillar. This revealed that Cu/Low-k WLP needs thick RDL to sustain the stresses imposed on RDL during TC test.
 
Figure 1. SEM planar view of the fine pitch copper pillar interconnects
Figure 2. Cross-section view of the Cu/Low-k WLP package with 300 um pitch copper pillar based interconnects
Figure 3. Cu/Low-k WLP package with 300 um pitch copper pillar based interconnects
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