The formation of ultra shallow and abrupt source/drain (S/D) junctions has always been one of the foremost issues in the scaling of the CMOS devices. The scaling of S/D junction depth results in extremely high parasitic resistance in respect to the channel resistance, and eradicates the otherwise expected performance improvement from the practice of scaling. Schottky S/D MOSFET architecture, which is the metallic S/D regions being direct contacting with the channel, provides shallow and abrupt junction interfaces with reduced parasitic resistance provided the Schottky barrier height ‘Fb’ is low to carrier injections.

Nickel monosilicide (NiSi), which provides low resistivity with low temperature process and high scalability, has emerged as the silicide of choice in the advanced planar CMOS for salicidation. However, being a mid-gap material it results in large barrier height and therefore is not suitable for Schottky S/D to channel junctions without some sort of barrier lowering technique such as dopant-segregation, Sulfur-passivation, or incorporation of interfacial oxide layer.

Based on IME’s Si nanowire device platform, using NiSi as Schottky material, IME researchers in collaboration with Nanyang Technological University have observed experimental evidences of Schottky barrier height lowering with reduction in nanowire channel thickness. Nanowire FETs with intentionally misaligned gate – one edge at 35 nm wider fin and other at 6 nm thin nanowire – in GAA architecture were fabricated to study the effect of size of the Schottky junction (Fig. a). When being characterised as the back-to-back diodes with gate floating, significant asymmetry in reverse leakage current is seen. This suggests the asymmetry of the barrier heights of the device. Form this unique characteristic, the Si nanowire p-FET exhibits near ideal sub-threshold turn-on behavior with low OFF state current and high ON state current. This is without the use of any barrier modification techniques, as demonstrated for the first time by the channel dimensional scaling.

Figure: (a) Schematic and (b) SEM image of the intentionally misaligned nanowire Schottky device after gate pattern transfer. Due to corner rounding (c) Two-terminal source to drain sweep showing rectifying characteristics. The inserts show the simplified Schottky barrier band diagrams at the source and drain, (d) Id-Vg and Id-Vd characteristics of the fabricated p-FET.