Ultra thin SiON gate dielectric is one of the most important materials in semiconductor device. Its performance, reliability, integrity, leakage and breakdown behavior have been studied for over 50 years and yet till today, the basic physical and atomistic understanding is still missing. Phenomenological models such as percolation model have been used to explain most of the electrical breakdown and reliability behaviors. However, the true nature of a breakdown percolation path remains to be a mystery.

In a collaboration with Nanyang Technological University, IME has studied the gate dielectric breakdown using unique TEM (transmission electron microscopy) capability and reported several newly identified gate dielectric related physical failure mechanisms.

The holy-grail in this study is to pin-point the breakdown percolation path down to nm scale and to clearly show its atomistic and chemical nature. With the help of a newly acquired monochromatic STEM (scanning TEM), the team has unveiled the mystery of gate dielectric breakdown.

DBIE accompanied by a gate dielectric breakdown indicates the existence of an invisible percolation path. EELS probing on the percolation path shows the atomistic and chemical nature of a gate dielectric breakdown.

The figure shows an HRTEM lattice image of a 2nmgate dielectric breakdown location. Dielectric Breakdown Induced Epitaxy (DBIE) is marked and identified. The percolation path directly on top of DBIE is invisible in ordinary TEM/STEM imaging condition. Monochromatic STEM and high resolution electron energy loss spectrometry (EELS) is used to study the percolation path. Preliminary results show that percolation path is a highly oxygen deficient sub-oxide path. Local band lowering may have occurred accompanied by the formation of defective bonds and intermediate states.

This new finding has important implication on our fundamental under-standing on gate dielectric breakdown and its reliability. Such understanding forms the foundation for process and technology engineers to push process limitation to the next level and helps to move semiconductor processes into the high-k metal gate domains.