IME researchers have fabricated a high-speed SONOS (silicon-oxide-nitride-oxide-silicon) non-volatile memory cell in gate-all-around vertically stacked twin Si-nanowire architecture reported earlier. The nanowire cell exhibits faster programme/erase (P/E) speed compared to the corresponding planar device.

Using F/N (Fowler-Nordheim) tunneling mechanism, a threshold voltage shift ‘ΔVTH’ of 2.6V and a programming window of 4.5V have been achieved with 1 µs for programming and 1 ms for erase at VGS = ± 11 V. At these P/E conditions, the planar device did not show appreciable change in the threshold voltage. The improvement in nanowire memory cells is originated from: i) increased electric field at the Si-SiO2 interface; ii) reduced effective tunnel barrier width and iii) low electric field in the blocking oxide, as analysed through simulation.

The P/E speed and threshold voltage shift could be improved further by depositing Si-nanocrystals (Si-NC) upon the trap layer. The nanocrystals provide additional accessible sites with an effective deeper trap energy level, which trap and de-trap more carriers with higher trapping efficiency. Utilising this engineered trap layer, for the same P/E conditions, the threshold voltage shift could be improved to 3.2V with a total P/E window of 6.25V. Based on the reported performance, the nanowire-based SONOS cell could be a potential candidate for future high-speed, low-voltage NAND-type non-volatile flash memory applications.

Figure: (a) Tilted view SEM image of vertically stacked twin-Si-nanowires; (b) High resolution TEM cross-section image of one of the channels of a fully processes device. Diameter of wire is ~ 5 nm and ONO stack is 4.5 nm/4.5 nm/8 nm (c) the simulated electric field distribution (top) and potential energy profile (centre) of the GAA nanowire and double-gate planar structures at VGS=11 V. For the GAA device (solid line), the electric field at the Si-SiO2 interface is almost three times larger as compared to the planar device (dashed line). Moreover, the effective barrier width of the GAA nanowire device is less than half the oxide physical thickness. (Bottom) Potential energy profile at VGS = - 11 V just before the start of the erasing process for the GAA nanowire device. An electron concentration of 5.3x107 cm-1, corresponding to an experimental shift of 2.6V in VTH, is assumed in the nitride layer. The barrier width for holes tunneling from the channel to the oxide is reduced due to the cylindrical architecture, thus increasing the erase speed.