Dr. Patrick Lo, Programme Director of IME's Nano-Electronics and Photonics Programme, presented an invited talk at the "International Symposium on Advanced Silicon-based Nano-Devices” sponsored by “Ultimately Integrated Devices and Systems” Research Committee in the Japan Society for the Promotion of Science on 9 November. The talk was attended by many Japanese research laboratories and universities who are key players in silicon nano-device area.

Dr. Lo's presentation was on “Si/SiGe Nanowire Technology Platform and Device Applications Based On Top-Down Approach”.  He gave a brief overview of the semiconductor nanowires, in particular Si- and Ge-nanowires, and summarised the status of CMOS-compatible nanowires devices. Results are based on the platform technology IME researchers have been building over the last two years.

To facilitate the realisation of controllable, scalable and increasing functionality, a top-down approach was adopted for the platform establishment on IME's 8" CMOS fabrication line. The talk discussed about the non-classical device structure evolution from Double-gated FinFET towards Gate-All-Around (GAA) nanowire FET.  In IME's study, GAA-nanowire FET was chosen as the test vehicle, since it is projected as the final architecture carrying the CMOS towards the end-of-the-roadmap for Si-devices.

Fabrication technology was presented with various gate-stacks options, and discussed with issues and potential solutions. Excellent transistor characteristics of GAA Si-nanowire FETs were illustrated with near-ideal sub-threshold, low DIBL, high ION/IOFF, accompanied with the demonstration of high gain CMOS Inverter. Finally, Ge-nanowire devices were also presented along with the well behaved vertically stacked device structures.