Around 120 people from the industry, A*STAR and IME attended the "IME Industry Night" held on 13 November 2007 at Amara Hotel. The Guest of Honour was Mr Lim Chuan Poh, Chairman of A*STAR.

The IME Industry Night provided an opportunity for IME partners and the microelectronics industry to come together to interact, network and share ideas. The event served to build closer ties between IME and the industry, and thank IME's long-term customers for their support. Some of the guests included top management from both overseas and local companies like Lightwire, Unisantis, Kinergy, SiMEMS, HealthSTATS and LNE Holdings.

Cocktail reception

The arrival of Guest of Honour, Mr Lim Chuan Poh

Mr Lim Chuan Poh (right) mingling with guests at the IME Industry Night.

The Industry Night also saw the launch of the 9th Electronics Packaging Research Consortium (EPRC 9). The EPRC was initiated in 1996 as a resource and cost sharing platform for electronics packaging R&D in pre-competitive areas of common needs. Over the years, more than 560 engineers from the industry have been attached to IME working on a total of 31 projects spanning the EPRC 1 to 8 programmes.

EPRC 9 is the largest EPRC programme ever with 31 memberships from 24 companies, both MNCs and SMEs, in four projects. The consortium consists of members from the IC packaging supply chain, such as wafer fab, packaging house, equipment and material suppliers. Amongst them, there are 21 multi-national companies and three SMEs. The new members include UMC, Samsung, Seiko, Finisar, Hitachi Cable, Kinergy, EVG, Tango Systems, BASF, Victrex and Sinyang. The member companies contribute application requirements, advance wafer technology, state of the art equipment and materials.

The members of EPRC 9 at the launch ceremony

The four projects of EPRC 9 are:

• Development of hybrid 3D stack and demonstration of optical interconnects - to demonstrate high frequency interconnect on FR4 optical PCB with low cost stacked dies;
• TSV technology for large die Cu/low K chip packaging- to develop TSV technology for large die Cu/low K chip with very fine pitch interconnection;
• Embedded micro wafer level packaging - to develop embedded wafer level packaging solution simultaneously achieving wafer level reconstruction of multiple chip using fan out interconnects, embedding passives design and fabrication, and assessment of electrical and reliability performance;
• Low temperature bonding for high density 3D interconnection - to develop a low temperature bonding for high density interconnection by Chip to Chip (C2C), Chip to Wafer (C2W) and Wafer to Wafer (W2W) bonding method to meet the higher reflow temperature.