The pursuit to integrate more and more devices for high functionality has been the driving force for the scaling of the CMOS technology and the phenomenal growth of the semiconductor industry. The dimension of the minimum feature size on the chip has decreased exponentially in time and the limits to scaling has become a hot research topic. Once devices below 100 nm were demonstrated in the research laboratories, it became clear that scaling may hit the "red-brick-wall" sooner than expected due to the short channel effects getting out of hand for the conventional planar transistors. The gate control over the channel becomes poorer with every technology node. This provides the motivation for extensive research in the novel (non-classical) device architectures.

FinFETs, Double-Gate MOSFETs, Tri-Gate MOSFETs, Omega-Gate MOSFETs, Gate-All-Around (GAA) MOSFETs are the results of research in this direction. GAA MOSFETs with cylindrical cross-section and narrow diameters, also known as nanowire MOSFETS, provides the best electrostatic control of the channel. Simulation results reported recently by various groups also support this.

While many researchers follow the approach of realising nanowire MOSFETs using the bottom-up techniques - the wires are grown using metal catalysts and CVD (chemical vapor deposition) process or vapor/liquid/solid phase (VLS) growth - IME has followed the top-down strategy. At IME, the nanowires are defined in a way compatible with standard CMOS technology using a combination of lithography and in situ silicon machining with the help of oxidation. Each approach has its own advantage - the bottom-up approach has potential for growth of nanowires of virtually unlimited materials while the top-down approach has the capability of quick integration in standard CMOS flow.

IME researchers have reported the next logical step, which is the monolithic integration of n- and p-MOS nanowire transistors using "conventional" top-down approach to realise CMOS logic gates. The basic building block, the ubiquitous inverter, is chosen as the test vehicle.

In the case of planar CMOS inverters, to compensates for the low value of the hole mobility for achieving symmetry in rise and fall times, with fixed length L, the width W for the p-MOS is kept typically 2 times that of n-MOS. As the diameters of the nanowires are the same for both n- and p-transistors, the L of the p-MOS is kept shorter than that of the n-MOS to achieve the symmetry in drive currents (Fig. 1). Interestingly, choosing a different channel diameter for n- and p-transistors is a distinct possibility with the top-down approach.

IME researchers have obtained encouraging results. Fig. 2 shows the inverter transfer characteristics with sharp transitions, large noise margins (NMH=0.53V and NML=0.41V) and a narrow transition region of ~150mV. Such high gains are the best amongst those reported so far for inverter logic based on nanowire MOSFETs. The individual devices comprising the inverter reported here exhibit excellent characteristics. The reasonable symmetry in the transfer characteristics indicates that choosing different lengths for n- and p- transistors helps in achieving the symmetric rise and fall times. Based on the CV/I metric, the projected gate delay for these inverters is expected to be of the order of a pico-second which is in line with the values projected by ITRS roadmap.

Further, the GAA nanowire inverters operate well with consistently large gains for low operating voltage. For a low VDD of 0.4V, a gain of ~14 is obtained.

Fig. 1: Inverter schematic. The P-MOSFET has shorter channel length as shown in the DRSEM image on the right.

Fig. 2: The transfer characteristics of the inverter with GAA nanowire MOSFETS. The inverters work excellently down to 0.4V of VDD.